1. Field of the Invention
The present invention generally related to a flash memory device. More particularly, the present invention relates to a NAND flash memory cell row and the manufacturing method thereof.
2. Related Art of the Invention
In recent years, flash memory device has become the main stream of the non-volatile memory device since that type of memory device allows for multiple data writing, loading and erasing operations. In addition, the stored data can be preserved even the power of the memory device is removed.
In a conventional flash memory device, generally the floating gate and control gate of are manufactured with doped amorphous silicon. In a stacked gate flash memory device, the control gate is disposed on the floating gate directly, a dielectric layer is disposed between the floating gate and the control gate, and a tunnel oxide layer is disposed between the floating gate and the substrate.
When a writing operation of data is provided for a flash memory, a bias voltage is applied to the control gate and the source/drain regions to inject the electrons into the floating gate. When the data stored in the flash memory is loaded, a working voltage is applied to the control gate, and the charging condition of the floating gate will effect the on/off of the channel below, wherein the on/off of the channel corresponds to the binary data “0” or “1”. When the data stored in the flash memory is erased, the voltage of the substrate, drain (source) or the control gate is increased, and the electrons in the floating gate will move into the substrate or drain (source) via the tunnel oxide layer due to the tunneling effect. The erase method is generally named as “substrate erase” or “drain (source) side erase”. Alternatively, the electrons in the floating gate can also move into the control gate via the dielectric layer.
In the operation of the flash memory, when the gate coupling ratio (GCR) between the floating gate and the control gate is increased, the working voltage of the operation reduces. Thus the operation speed and efficiency of the flash memory increases drastically. The method of increasing the gate coupling ratio includes the increasing of the overlap area between the floating gate and the control gate. However, when the size of the integrated circuit device is minimized, the junction area of the conventional control gate and floating gate is also reduced; thus, the gate coupling ratio and the performance of the memory device is reduced.
Further, the conventional flash memory array includes the NOR array structure and the NAND array structure. Since in the NAND array structure, the memory cells are connected in series, the integration of the NAND array structure is larger than that of the NOR array structure. However, the writing and the loading procedure of the memory cell of the NAND array structure is more complex. For example, the programming and erase operation of the memory cell of the NAND array structure are all performed by the tunnel F-N (Fowler-Nordheim) tunneling effect, to inject electrons into the floating gate via the tunnel oxide layer, and to pull out electrons from the floating gate to the substrate via the tunnel oxide layer. Therefore, the tunnel oxide layer will be damaged under high voltage operation and the stability will be reduced. Moreover, since a lot of memory cells are connected in series in the NAND array, the loading current of the memory cell is reduced; thus, the operation speed and the performance of the memory cell are also reduced.